The present invention relates to a method and/or architecture for decoding variable length code symbols generally and, more particularly, to a method and/or architecture for a multi-symbol variable length code decoder.
In digital data (i.e., audio, video, etc.) transmission systems, data is encoded prior to being transmitted to a receiver. The receiver decodes the encoded digital data. The decoded digital data is then output to a subsequent signal processing stage. To increase the data throughput and memory efficiency of such systems, statistical compression algorithms are used to compress and encode the digital data.
Compressing the data typically results in data streams that are segmented into variable length code words rather than fixed length code words. Variable length decoders are used to decode the variable length code words comprising the compressed data stream. Conventional methods for decoding a sequence of variable length code words include a tree searching algorithm and a table look-up technique.
The tree searching algorithm performs a bit-by-bit search through a code tree to find the end and value of each code word in the input bit stream. Decoding a bit stream using the tree searching algorithm can be too slow for many high speed applications, since the decoding operation is performed at the bit rate rather than at the symbol rate.
To increase the data throughput of a variable length decoder (VLD), the table look-up technique can be used. A conventional table look-up decoder decodes one code word per clock cycle regardless of the code word bit length, thereby increasing the data throughput of the decoder relative to the tree searching algorithm decoder. The actual speed of operation of conventional table look-up decoders can be limited by propagation delay within the decoder.
In addition to technical problems associated with implementing high throughput VLDs, interfacing a high-speed VLD with a large capacity rate buffer can be expensive with currently available memory technology. The problem becomes more severe if price is an issue, since faster and more expensive memory devices such as static random access memories (SRAMs) and synchronous dynamic random access memories (SDRAMs) are used rather than slower and cheaper memory devices such as asynchronous DRAMs. The price of the memory can be a particularly important consideration for a consumer product.
It would be desirable to have a variable length code decoder having a data throughput that is adequate for processing high speed digital data (e.g., video), but at a lower clock rate.
The present invention concerns an apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for a multi-symbol variable length code decoder that may (i) provide high throughput, (ii) decode one or more symbols per clock cycle, (iii) decode short symbols via a hardwired lookup table, (iv) use hardware to determine a first symbol length and/or (v) use a first symbol length to determine a starting point of a second symbol.